@ARTICLE{Kwiatkowski_Paweł_Employing_2019,
 author={Kwiatkowski, Paweł},
 volume={vol. 26},
 number={No 4},
 journal={Metrology and Measurement Systems},
 pages={631-643},
 howpublished={online},
 year={2019},
 publisher={Polish Academy of Sciences Committee on Metrology and Scientific Instrumentation},
 abstract={The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.},
 type={Article},
 title={Employing FPGA DSP blocks for time-to-digital conversion},
 URL={http://ochroma.man.poznan.pl/Content/114023/PDF/04_MMS_4_INTERNET.pdf},
 doi={10.24425/mms.2019.130570},
 keywords={time-to-digital converter, time coding line, time interval counter, digital signal processing, field-programmable gate array},
}