Tytuł artykułu

Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs

Tytuł czasopisma

International Journal of Electronics and Telecommunications

Rocznik

2010

Wolumin

vol. 56

Numer

No 4

Autorzy

Rawski, Mariusz

Wydział PAN

Nauki Techniczne

Wydawca

Polish Academy of Sciences Committee of Electronics and Telecommunications

Data

2010

Identyfikator

DOI: 10.2478/v10177-010-0045-9 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)

Źródło

International Journal of Electronics and Telecommunications; 2010; vol. 56; No 4

Referencje

Meyer-Baese U. (2004), Digital Signal Processing with Field Programmable Gate Arrays. ; Parhi K. (1999), VLSI Digital Signal Processing Systems: Design and Implementation. ; Eshtawie M. (2006), On-line DA-LUT architecture for high-speed high-order digital FIR filters, null, 5. ; Meher P. (2006), Hardware-efficient systolization of DA-based calculation of finite digital convolution of finite digital convolution, IEEE Transactions on Circuit and Systems II: Express Briefs, 53, 8, 707. ; Xie J. (2010), FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures, Microelectronics Journal, 41, 6, 365. ; Cong J. (2000), Synthesis for FPGas with embedded memory blocks, FPGA. New York, 75. ; Krishnamoorthy S. (2003), Technology mapping algorithms for hybrid FPGAs containing lookup tables and plas, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22, 5, 545. ; Rawski M. (2005), The influence of functional decomposition on modern digital design process, Design of Embedded Control Systems, 193. ; Sasao T. (2005), On LUT cascade realizations of fir filters, null, 467. ; Rawski M. (2005), Efficient implementation of digital filtres with use of advanced synthesis methods targeted FPGA architectures, null, 460. ; Jamieson P. (2005), A verilog RTL synthesis tool for heterogeneous FPGAs, null, 305.