Tytuł artykułu

Synthesis and Implementation of Reconfigurable PLC on FPGA Platform

Tytuł czasopisma

International Journal of Electronics and Telecommunications

Rocznik

2012

Wolumin

vol. 58

Numer

No 1

Autorzy

Milik, Adam ; Hrynkiewicz, Edward

Wydział PAN

Nauki Techniczne

Wydawca

Polish Academy of Sciences Committee of Electronics and Telecommunications

Data

2012

Identyfikator

DOI: 10.2478/v10177-012-0012-8 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)

Źródło

International Journal of Electronics and Telecommunications; 2012; vol. 58; No 1

Referencje

Berger H. (2001), Automating with STEP 7 in LAD and FBD - SIMATIC S7-300/400 Programmable Controllers. ; Michel G. (1992), Programmable Logic Controllers - Architecture and Applications. ; Chmiel M. (2005), Concurrent operation of the processors in bit-byte CPU of a PLC, null. ; Chmiel M. (2005), Design of Embedded Control Systems, 231, doi.org/10.1007/0-387-28327-7_20 ; Chmiel M. (2006), Compact PLC with event-driven program tasks execution, null, 99. ; Devadas S. (1994), Logic Synthesis. ; Gajski D. (1994), High-Level Synthesis. Introduction to Chip and System Design. ; A. Mishchenko. (2010) Abc: A system for sequential synthesis and verification. [Online]. Available: <a target="_blank" href='http://www.eecs.berkeley.edu/alanmi/abc/'>http://www.eecs.berkeley.edu/alanmi/abc/</a> ; Milik A. (2000), PID module for reconfigurable logic controller, null. ; Milik A. (2006), High level synthesis - reconfigurable hardware implementation of programmable logic controller, null. ; Shanta S. (2005), A new generation of PLC-an FPGA based PLC, null, 2367. ; Yadong L. (2005), Model-driven programmable logic controller design and FPGA-based hardware implementation, null, 81. ; Xilinx, <i>DS-099, Spartan-3 FPGA Family, ver.2.1.</i> Xilinx, 2006. ; <i>International Standard IEC 1131, Programmable Controllers</i>, International Electronics Commission Std. IEC, Geneva, 1992. ; Welch J. (1992), Translating unrestricted relay ladder logic into boolean form, Computers in Industry, 20, 45, doi.org/10.1016/0166-3615(92)90126-8 ; Ichikawa S. (2006), Converting PLC instruction sequence into logic circuit: A preliminary study, null, 4, 2930. ; Du D. (2010), A study on the generation of silicon-based hardware PLC by means of the direct conversion of the ladder diagram to circuit design language, 49. ; Du D. (2009), Study on LD-VHDL conversion for FPGA-based PLC implementation, The International Journal of Advanced Manufacturing Technology, 40, 1181, doi.org/10.1007/s00170-008-1426-4 ; Aho A. (1986), Compilers: Principles, Techniques, and Tools. ; Akers S. (1978), Binary decision diagrams, IEEE Transactions on Computers, C-27, 509, doi.org/10.1109/TC.1978.1675141 ; Bryant R. (1986), Graph based algorithms for boolean function manipulation, IEEE Transactions on Computers, C-35, 677, doi.org/10.1109/TC.1986.1676819 ; Minato S.-I. (1995), Binary Decision Diagrams and Applications For VLSI CAD. ; Xilinx, <i>UG073, XtremeDSP for Virtex-4 FPGAs User Guide.</i> Xilinx, 2007. ; Xilinx, <i>UG389, Spartan-6 FPGA DSP48A1 Slice.</i> Xilinx, 2009. ; Xilinx, <i>DS302, Virtex-4 FPGA Data Sheet: DC and Switching Characteristics.</i> Xilinx, 2007. ; Xilinx, <i>DS162 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.</i> Xilinx, 2011. ; Hachtel G. (1996), Logic synthesis and verification algorithms. ; Hassoun S. (2002), Logic synthesis and verification, doi.org/10.1007/978-1-4615-0817-5 ; Mishchenko A. (2007), Combinational and sequential mapping with priority cuts, null, 354. ; Bibero R. (1990), Microprocessors in Instruments and Control.