Title

Decomposition of multi-output functions oriented to configurability of logic blocks

Journal title

Bulletin of the Polish Academy of Sciences Technical Sciences

Yearbook

2017

Volume

65

Issue

No 3

Authors

Kubica, M. ; Kania, D.

Divisions of PAS

Nauki Techniczne

Coverage

317-331

Date

2017

Identifier

DOI: 10.1515/bpasts-2017-0036 ; ISSN 2300-1917

Source

Bulletin of the Polish Academy of Sciences: Technical Sciences; 2017; 65; No 3; 317-331

References

Kubica (null), Area - oriented technology mapping for LUT - based logic blocks of and ( in press ), International Journal Applied Mathematics Computer Science, 27, 2017. ; Lai (1996), OBDD - based function decomposition : Algorithms and implementation IEEE Transactions on Computer - Aided, Design, 15, 977. ; Mishchenko (2007), Improvements to technology mapping for LUT - based FPGAs IEEE Aided Design Integr Circuits, Trans Comput Syst, 26, 240. ; Liang (2010), ALMmap : Technology mapping for FPGAs with adaptive logic modules ACM International Conference on Computer - Aided Design, IEEE, 143. ; Yang (2002), BDS : A BDD - based logic optimization system IEEE Comput - Aided Design Integr Circuits, Trans Syst, 21, 866. ; Borowik (2011), On memory capacity to implement logic functions Computer Systems Theory - EUROCAST Part II pp eds Arencibia Springer - Verlag, Aided, 343. ; Kania (2007), Logic synthesis for PAL - based CPLD - s based on two - stage decomposition The of Systems and, Journal Software, 80, 1129. ; Abouzeid (1993), Input - driven partitioning methods and application to synthesis on table - lookup - based FPGAs IEEE on, Trans CAD, 12, 913. ; Muma (2008), Combining ESOP minimization with BDD - based decomposition for improved FPGA synthesis Canadian of Electrical and Computer, Journal Engineering, 33, 177. ; Kania (2015), Logic decomposition for PAL - based CPLDs Journal of Circuits , Systems and, Computers, 24, 1. ; Kubica (2016), SMTBDD : New form of BDD for logic synthesis of Electronics and Telecommunications, International Journal, 62, 33. ; Chang (1996), Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams IEEE Transactions on Computer - Aided, Design, 15, 1226. ; Yamashita (1998), New methods to find optimal non - disjoint bi - decompositions Design of the ASP -, Automation Conference Proceedings DAC, 98, 59. ; Cheng (2008), DDBDD : Delay - driven BDD synthesis for FPGAs IEEE Transactions on Computer - Aided Design of Integrated Circuits and, Systems, 27, 1203. ; Cheng (2007), DDBDD : Delay - driven BDD synthesis for FPGAs th ACM / Design Automation Conference, IEEE, 44, 910. ; Muma (2005), A new logic synthesis ExorBDS on Electrical and, Canadian Conference Computer Engineering, 816. ; Łuba (1995), A general approach to Boolean function decomposition and its applications in FPGA - based synthesis VLSI design Special Issue on Decompositions in VLSI, Design, 3, 289. ; Opara (2010), Decomposition - based logic synthesis for PAL - based CPLDs of and, International Journal Applied Mathematics Computer Science, 20, 367. ; Kania (2000), Decomposition - based synthesis and its application in PAL - oriented technology mapping Proceedings of the th, Euromicro Conference, 26. ; Perkowski (1999), Graph coloring algorithms for fast evaluation of curtis decompositions th ACM DAC, IEEE, 36, 99. ; Vemuri (2002), BDD - based logic synthesis for LUT - based FPGAs ACM Design, Trans Autom Electron Syst, 7, 501.