Title

Design Protection Using Logic Encryption and Scan-Chain Obfuscation Techniques

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2019

Volume

vol. 65

Issue

No 3

Authors

Deepak, V.A. ; Priyatharishini, M. ; Nirmala Devi, M.

Keywords

Hardware Security ; Obfuscation ; Logic Encryption ; Scan-Chain

Divisions of PAS

Nauki Techniczne

Coverage

389-396

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2019.09.06

Type

Artykuły / Articles

Identifier

DOI: 10.24425/ijet.2019.129790 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)

Source

International Journal of Electronics and Telecommunications; 2019; vol. 65; No 3; 389-396