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Title

Improving LUT count of FPGA-based sequential blocks

Journal title

Bulletin of the Polish Academy of Sciences Technical Sciences

Yearbook

2021

Volume

69

Issue

2

Affiliation

Barkalov, Alexander : University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland ; Barkalov, Alexander : Vasyl’ Stus Dohetsk National University, 21, 600-richya str., Vinytsia, 21021, Ukraine ; Titarenko, Larysa : University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland ; Titarenko, Larysa : Kharkiv National University of Radio Electronics, Nauky avenye, 14, 6166, Kharkiv, Ukraine ; Mazurkiewicz, Małgorzata : University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland ; Krzywicki, Kazimierz : The Jacob of Paradies University, ul. Teatralna 25, 66-400 Gorzów Wielkopolski, Poland

Authors

Barkalov, Alexander ; Titarenko, Larysa ; Mazurkiewicz, Małgorzata ; Krzywicki, Kazimierz

Keywords

FPGA ; LUT ; Mealy FSM ; synthesis ; structural decomposition ; product terms ; partition

Divisions of PAS

Nauki Techniczne

Coverage

e136728

Bibliography

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Date

08.03.2021

Type

Article

Identifier

DOI: 10.24425/bpasts.2021.136728

Source

Bulletin of the Polish Academy of Sciences: Technical Sciences; 2021; 69; 2; e136728
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