Title

Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2025

Volume

vol. 71

Issue

No 2

Authors

Satyanarayana, D. ; Chennakesavulu, M. ; Fouzia Sulthana, N. ; Upendra, K. ; Sashidhar, D. ; Ramachandra Reddy, K. ; Naga Sai Vikranth, N. ; Devendra, V.

Affiliation

Satyanarayana, D. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Chennakesavulu, M. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Fouzia Sulthana, N. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Upendra, K. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Sashidhar, D. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Ramachandra Reddy, K. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Naga Sai Vikranth, N. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Devendra, V. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India

Keywords

Low power ; Full adder ; Multiplier ; Delay ; PassTransistor

Divisions of PAS

Nauki Techniczne

Coverage

483-488

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

4.06.2025

Type

Article

Identifier

DOI: 10.24425/ijet.2025.153595