Details Details PDF BIBTEX RIS Title PyHLS: Intermediate Representation for Versatile High-Level Synthesis Journal title International Journal of Electronics and Telecommunications Yearbook 2025 Volume vol. 71 Issue No 4 Authors Cieszewski, Radosław Affiliation Cieszewski, Radosław : Faculty of Electronics and Information Technology, Institute of Electronics Systems, Warsaw University of Technology, Poland Keywords High-Level Synthesis ; intermediate representation ; FPGA ; Real-Time Systems ; triggers ; microinstructions ; modularity ; AI tiles Divisions of PAS Nauki Techniczne Coverage 1-7 Publisher Polish Academy of Sciences Committee of Electronics and Telecommunications Date 22.10.2025 Type Article Identifier DOI: 10.24425/ijet.2025.156531 <div class="test"></div>